![]() ![]() Compliance Voltage of Current Source or Current Sink Relative to the emitter, as shown for the pnp transistor, when the base-emitter voltage is greater than the collector-emitter voltage the BJT device is operating in the saturation region.ģ. ![]() You pick your own values for V margin and current and RdsOn. 50 mOhm FET regulated by a 50 mV current sense shunt at max current and an Op AMp to regulate the FET bias so you get < 100mV drop total. How do you choose a LED switch for 3.3V when the LED uses up 3.1V and the Vce(sat) is > 0.2VĬompute required Rs for current sensing or voltage drop and choose a FET switch with much lower resistance.Į.g. The rated Vce(sat) is just to the right of the steepest curve where the Rce changes from 180 mΩ to 333 mΩ with a higher current ratio. Then the steepest part of the curves are the lowest resistance as a switch. This turns out to be about 10% of the max linear hFE ratio when used as a current amplifier. For efficiency reasons, they chose the optimum current ratio within reasonable heat rise. The graphs show it but it is only one point in magenta. ![]() Why does the datasheet state that the saturation voltage occurs when VCE=0.16V (to a max of 0.25V) but the corresponding graph does not agree with this? However they rated Vce(sat) at 50:1 current ratio. This one is 200 typical in the low current range but only 80 in the 20 mA range. Vce(sat) tends to be rated at 10% of the max linear hFE. (sorry for quick and dirty curves added to show hFE and Rce(sat) with the current ratio) But the horizontal slope acts as a (lossy) current sink and the more vertical slopes act as a lossy switch (resistor). The curve tracer type slopes show constant base current with Vce vs Ic. Your interpretation of the \$V_\$, because the transistor is saturated in this regime. ![]()
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